A 14-bit 100 MS/s two-step split SAR ADC with a low-power high-linearity residue amplifier

Abstract High-speed, high-precision and low-power-consumption Analog-to-Digital Converter is widely used in particle physics detectors. We develop a two-step sub-SAR ADC to achieve low power consumption, using pipeline principle to improve the speed on a 55 nm CMOS process. We employ in-stage and between-stage redundancy to improve the SNDR. We choose a gain-boosted operational amplifier without any internal phase compensation as the residue amplifier to decrease the power consumption. The simulation results indicate that the SNDR can be up to 84.2 dB with 14 bits, and the power consumption is about 12.8 mW.