Ph.D. Project: Floorplan Quality Prediction for HLS Design Exploration on Multi-Die FPGA

High-level synthesis (HLS) and multi-die FPGAs are widely used for large-scale accelerators. To address the cross multi-die boundary delays and local congestion issues in HLS designs on multi-die FPGAs, a coarse-grained floorplan and pipeline method was proposed to improve frequency performance. However, achieving better frequency performance requires iterative implementation in Vitis to adjust the parameters, leading to significant time overhead. To accelerate this tuning process, this paper proposes a floorplan quality predictor based on a graph neural network for each slot on FPGA, achieving accuracy rates of 88.63% and 89.68% in high-level congestion and critical resource, respectively. Compared with the traditional tuning process, we reduce the time overhead from 7 hours to millisecond-level and achieve a 25 % improvement in WNS performance in the tuning case.