FREEDOM: FPGA-Based Hardware Redaction Emulator

Most VLSI design companies are now fabless. This forces them to rely on complex international supply chains that can compromise their Intellectual Property (IP). One popular approach to address this is through logic locking [1], [2]. One of the problems with traditional locking mechanisms is that the locking circuitry is built into the netlist that the (HW) design company delivers to the foundry, which has now access to the entire design, including the locking mechanism [3]. This implies that they could potentially tamper with this circuitry or reverse engineer it to obtain the locking key. An alternative approach is to redact a portion of the hardware design by mapping it to an embedded FPGA (eFPGA). The unprogrammed design is then sent to be fabricated at an untrusted fab, which can now not reverse engineer the design because they do not have the bitstream configuration that makes the entire chip operate correctly. The bitstream acts in this case as the locking key. Hardware redaction is nevertheless not 100% secure, and different attacks have already been proposed [4]. The main problem with most of these attacks is that they require long simulation times, but in reality, when applied to the actual hardware, are executed much faster. Thus, in this work, we propose an open-source FPGA-based hardware redaction framework to speed up new attacks with the ultimate goal of learning how to build more robust hardware redaction systems. The framework is composed of an automated ASIC and FPGA partitioning tool, the mapping of these parts onto a low-cost FPGA board (Terasic DE10-SoC[5]) and a library of software APIs that run on the embedded processor of the FPGA in order to launch attacks onto the redacted systems mapped onto the FPGA fabric. The experimental results show that the emulation platform is orders of magnitude faster than a pure simulation-based approach while also scaling much better. The entire platform is available online at https://github.com/chaitalisathe/FREEDOM.

Authors

Institutions

Publication Details

Published
2025-05-04
DOI
https://doi.org/10.1109/fccm62733.2025.00027
Primary Topic
Embedded Systems Design Techniques
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

FREEDOM: FPGA-Based Hardware Redaction Emulator

Benjamin Carrión Schäfer, Yiorgos Makris, Chaital. G. Sathe
Embedded Systems Design Techniques
article

FREEDOM: FPGA-Based Hardware Redaction Emulator

Benjamin Carrión Schäfer, Yiorgos Makris, Chaital. G. Sathe
article en

Abstract

Most VLSI design companies are now fabless. This forces them to rely on complex international supply chains that can compromise their Intellectual Property (IP). One popular approach to address this is through logic locking [1], [2]. One of the problems with traditional locking mechanisms is that the locking circuitry is built into the netlist that the (HW) design company delivers to the foundry, which has now access to the entire design, including the locking mechanism [3]. This implies that they could potentially tamper with this circuitry or reverse engineer it to obtain the locking key. An alternative approach is to redact a portion of the hardware design by mapping it to an embedded FPGA (eFPGA). The unprogrammed design is then sent to be fabricated at an untrusted fab, which can now not reverse engineer the design because they do not have the bitstream configuration that makes the entire chip operate correctly. The bitstream acts in this case as the locking key. Hardware redaction is nevertheless not 100% secure, and different attacks have already been proposed [4]. The main problem with most of these attacks is that they require long simulation times, but in reality, when applied to the actual hardware, are executed much faster. Thus, in this work, we propose an open-source FPGA-based hardware redaction framework to speed up new attacks with the ultimate goal of learning how to build more robust hardware redaction systems. The framework is composed of an automated ASIC and FPGA partitioning tool, the mapping of these parts onto a low-cost FPGA board (Terasic DE10-SoC[5]) and a library of software APIs that run on the embedded processor of the FPGA in order to launch attacks onto the redacted systems mapped onto the FPGA fabric. The experimental results show that the emulation platform is orders of magnitude faster than a pure simulation-based approach while also scaling much better. The entire platform is available online at https://github.com/chaitalisathe/FREEDOM.

The University of Texas at Dallas (US)
Openalex Percentile: Top 89%
Embedded Systems Design Techniques
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.

FREEDOM: FPGA-Based Hardware Redaction Emulator — Benjamin Carrión Schäfer, Yiorgos Makris, et al. · (2025) | TGRS Research Map | TGRS