Toward Reconfigurable In-Pixel Computing: A Fault-Tolerant Design Flow for Machine Learning Accelerators: (Invited Paper)

In-pixel computing has emerged as a promising paradigm for edge machine learning, enabling computations directly within sensors to achieve low latency and real-time performance. However, current hardware designs generated by high-level synthesis (HLS) tools often lack flexibility and adaptability to new tasks. Additionally, robustness against single-event upsets (SEUs) in harsh radiation environments remains a critical requirement. To overcome these limitations, we propose a fault-tolerant framework that evaluates bit-level susceptibility of neural network weights, selectively applying Triple Modular Redundancy (TMR) to critical components. Our methodology integrates custom memory modules into the HLS workflow, enabling post-deployment reconfiguration for task updates and adaptive fault protection. Moreover, we introduce a TMR-aware back-end synthesis flow that dynamically allocates redundancy according to user-defined area and power constraints, achieving scalable and efficient hardware implementations.