Ph.D. Project ARIES: Efficient Mapping and Automated Compilation for AMD Versal Devices

As AI continues to grow, modern applications are becoming more memory and computation intensive, driving the development of specialized AI chips to meet these demands. AMD Versal ACAP devices serve as a promising heterogeneous solution for continuous compute scaling. However, heterogeneity presents challenges not only in achieving high-performance mapping solutions but also in providing a programming abstraction that ensures high productivity. If these challenges are not effectively addressed, they will hinder the widespread adoption of these heterogeneous architectures by experts from other domains beyond hardware expertise. We are among the first to explore efficient mapping solutions for this heterogeneous system. We propose a series of works (FPGA'23 [1], DAC‘23 [2], TRETS‘24 [3], FPGA‘24 [4], TCAD‘24 [5]), which thoroughly investigate the design space for modern transformer-based workloads by mapping different layers to various system components, such as CPUs, FPGAs, and AIEs, while analyzing the trade-offs between latency and throughput. Additionally, to significantly enhance programming productivity on these heterogeneous systems, we are the first to introduce ARIES (FPGA'25 [6] Best Paper Nominee), a multi-level intermediate representation (MLIR)-based compilation framework that proposes a unified intermediate representation (IR) for the end-to-end application deployment on AIE architectures.