Ph.D. Project Hardware-Aware Neural Networks

The challenges of deploying overparameterized neural networks (NNs) on resource-constrained hardware necessitate innovative approaches that transcend traditional precision and overparameterization paradigms. Our research explores NN design with a deep awareness of hardware limitations, rethinking traditional approaches to radically reduce inference cost on field-programmable gate arrays (FPGAs). We focus on developing hardware-aware NNs that integrate multiple levels of precision and expressivity to enhance performance. Our PolyLUT, NeuraLUT and NeuraLUT-Assemble methodologies leverage the flexibility of Boolean lookup tables (LUTs) to enhance network expressivity and efficiency. By strategically integrating diverse data representations and arithmetic operations, these models redefine NN design, offering a pathway to highly efficient, hardware-optimized networks that do not compromise on accuracy or generalization. Future research will aim to investigate how these models scale up to more complex tasks, even broadening the scope to language models, where LUT-based approaches could offer significant improvements in memory efficiency and inference speed. Moreover, along the practical advancements in efficient AI design, we plan to advance the theoretical understanding of these unconventional topologies.