Transfer Learning on the Edge for a Wireless Application Using an SoC Platform
Edge devices with limited resources are critical components of modern wireless communication systems. As communication environments become increasingly complex, neural networks are playing a larger role in processing large amounts of data to enable Machine Learning (ML) within these systems. While most FPGA-based accelerators focus on neural network inference, deploying the training phase on resource-constrained edge devices remains a significant challenge. Training on a System on Chip (SoC) that combines ARM processors with FPGA fabric provides unique benefits, including the ability to quickly adapt models to dynamic environments. This work leverages the Tiny Transfer Learning (TinyTL) framework for on-device training, which allows edge devices to continuously adapt neural network models to new data with minimal memory requirements. To the best of our knowledge, this is the first use of a heterogeneous platform to accelerate training using TinyTL. We present the Accelerating TinyTL-based Digital PreDistortion (ATDPD) system, designed to adapt to varying behaviors of power amplifiers in wireless communication systems and implement it on an AMD RFSoC. Our heterogeneous approach achieves comparable training accuracy to ARM-based systems, while accelerating the training phase by more than 20%.
Authors
- Yiyue Jiang
- Miriam Leeser (ORCID: https://orcid.org/0000-0002-5624-056X)
- John Dooley (ORCID: https://orcid.org/0000-0002-2638-2399)
- Z. Ren
- Jonathan Guimaraes Ribeiro
- Aidan Edward Colgan
Institutions
- Boston University (US)
- National University of Ireland, Maynooth (IE)
Publication Details
- Published
- 2025-05-04
- DOI
- https://doi.org/10.1109/fccm62733.2025.00064
- Primary Topic
- VLSI and Analog Circuit Testing
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- MathWorks