RRAM-Based NVFF: Harnessing AWT and Differential Power-Up for Enhanced Power, Speed, and Reliability

Nonvolatile flip-flop (NVFF) based on resistive random access memory (RRAM) is applicable in low-power and rapid-response scenarios. This article proposes a circuit design that incorporates a differential power-up strategy and introduces an autowrite termination (AWT) mechanism specifically in the RESET phase. The initial state of RRAM is set to a low-resistance state (LRS), which is matched without applying voltage to RRAM when the output (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i>) is low voltage. Simulation results show that with write times reduced from 700 units to an average of 30 units, this technology offers an 8.5× power advantage over the 20T1R NVFF without AWT. It also diminishes the duration of voltage stress on the RRAM in the RESET phase by 95.7%. Differential power-up further reduces the data restore error rate to 0.15%. Restore power consumption is reduced by 37.8%, and restore time is significantly shorter. The feedback loop increases the area overhead of this design by 10%, but the energy delay area product (EDAP) shows that this design achieves a 12.5× performance advantage. Additionally, the effect of area overhead decreases as the number of NVFF cells increases, and this advantage is even more pronounced.