Superior QLC Retention Enhancement of a Large Memory Window FEFET Through Gate Stack Engineering

3-D NAND flash cells with ferroelectric field-effect transistors (FEFETs) have gained significant attention due to emerging challenges in 3-D NAND technology. Although metal–insulator–ferroelectric–insulator–semiconductor (MIFIS) structures provide large memory windows (MWs), FEFET is still under extensive research and faces critical issues such as data retention, write endurance, disturbance, variability, scalability, gate stack thickness, write voltage, and thermal stability of FE-HfO<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>2</roman></sub>. Here, we propose a novel gate stack, metal–insulator-high <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> insulator–ferroelectric–insulator–semiconductor (MIKFIS) to address these challenges. The MIKFIS FEFET achieves a large MW of 12.2 V and demonstrates highly enhanced quad-level-cell (QLC) data retention at both 24 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C and 85 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">∘</sup>C. Moreover, MIKFIS offers additional benefits, including reduced monoclinic-(m-) phase formation, reduced gate stack thickness, decreased equivalent oxide thickness (EOT), and enhanced FE switching. The origin of the superior retention of MIKFIS is investigated using a revised measurement technique developed to accurately extract polarization.