ASTEF: FPGA-Based Enhancement of Event Camera Performance in Low-Light Conditions

In low-light environments, event cameras suffer from sparse and noisy outputs. We propose ASTEF, a near-sensor FPGA architecture using adaptive temporal filtering and dynamic thresholding to improve signal quality under poor illu-mination. Implemented on the Zynq-7000 SoC, ASTEF reduces Slice LUTs by 83.91% and 93.49% compared to HMAX and HARP, respectively, while lowering dynamic power by up to 83.88%. A Python-based simulator further verifies its robustness, outperformina ROI-based models in dark scenes.