Impact of Layout on the RF Performance of Vertical In–Ga–As Nanowire MOSFETs

High-speed vertical In–Ga–As nanowire MOS field-effect transistor (MOSFET) measurements were analyzed through parametric layout models. Measurements from small and large transistors were used to fit dependencies on the number of gate fingers and the number of wires per finger. Extrapolations via intrinsic and parasitic elements reveal the optimal layout for peak frequency performance. To achieve a scalable technology platform, the process flow was here also reworked and simplified. In conjunction with refined feeder patterning, addition of a drain spacer, and reduced gate lengths previously demonstrated, the results indicate a viable path for strongly improved frequency performance in the technology.