Photon Event Summation and External Readout for Fill Factor Preservation in 32×32 FSI SPAD Array

Single-photon avalanche diodes (SPADs), integrated in CMOS technology, offer high-gain detection of low-intensity optical signals. SPADs are widely adopted in imaging systems, including both 2D and 3D depth sensing. As SPAD arrays scale to higher resolutions, backside illumination (BSI) is one approach to improving fill factor (FF) and routing, though it increases fabrication complexity. Alternatively, in frontside illumination (FSI), the integration of circuitry within the pixel area results in a significant reduction of the FF. Thus, this brief proposes an external counter architecture with a photon event summing and coincidence detection scheme. Unlike conventional FSI designs, it preserves FF and improves routing efficiency, which facilitates scalability. This architecture is well suited for SPAD-based imaging and 3D sensing, which require high pixel resolution and compact signal integration.