Improvement of leakage off current of MOSFET with Si and Ge based Structure

In contemporary nano-scale CMOS technology, leakage current has emerged as acritical limiting factor in the optimization of device performance and energy efficiency.This study presents the simulation-based investigation into the suppression of off-state leakage current in Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs).The short-channel effect analysis is done to understand leakage mechanisms such as subthreshold conduction, gate-induced drain leakage (GIDL), and tunnelling.These phenomena are analytically addressed by modifying threshold voltage behaviour through channel engineering and high- dielectric integration.Implementation of structural optimizations is done through the use of retrograde well doping, lightly doped drain profiles within the TCAD framework.Simulation results demonstrate a significant reduction in off-state current in magnitude, validating the effectiveness of the proposed design modifications.This synergistic approach and device-level simulation offers a viable pathway toward leakage minimization in advanced MOSFET architectures.In this paper, extra p type with lightly doped region is introduced in between channel and drain for reducing gate leakage current.Double gates are used for better control over channel current.