A Perspective on Interconnect Scaling Challenges in the NanoStack Transistor Era : AP/DFM: Advanced Patterning / Design for Manufacturing (Design-Technology Co-Optimization)

This paper explores various design and technology co-optimization (DTCO) challenges as they apply to back-end-of-line (BEOL) interconnects used for vertically-stacked Nanosheet ("NanoStack") transistor architectures. Aggressive interconnect pitch scaling may drive the industry toward direct-etch patterning of lines with embedded air gaps, which pose challenges in terms of process integration as well as variability. Backside power delivery network (BSPDN) architectures remove power rails from frontside interconnect track plans but pose stringent requirements on ground rules (such as tip-to-end and via enclosures) which may require cut patterning. Certain architectures, such as NanoStack transistors and/or skip-level interconnect vias, require extreme high aspect ratio etch and metallization with extreme resistance sensitivity to post-metallization vertical profile. Looking to the future, new classes of materials have been identified which possess fundamentally different resistivity scaling mechanisms than conventional metals, though the CMOS-compatible integration of these materials remains a question. These challenges and more are discussed in the context of advanced interconnects for optimized power, performance, area and cost (PPAC) in next-generation semiconductor technologies.