Silicon-Germanium (SiGe) Epitaxial Growth for Enhanced Device, Yield, and Uniformity

SiGe for Source/Drain (S/D) regions has been widely analyzed in FinFET technology. The quality of the SiGe within the S/D of a pFET FinFET determines the devices performance, chip level yield, and the within wafer uniformity (WiW). In this study, two SiGe Epi growth processes are compared. The enhanced process results in improved performance, chip level yield, and uniformity compared to the reference. +5% device performance, +0.25% wafer edge Yield gain, and -10% Freq/-5% Iddq on-chip level uniformity sigma reduction are successfully demonstrated.