Training-free and stochastic magnetic tunnel junction-based restricted Boltzmann machine for Boolean satisfiability problem

Traditional processors based on the von Neumann architecture are not efficient when dealing with combinatorial optimization problems, which has led to the proposal of unconventional algorithms and domain-specific computing architectures. Using probabilistic computing to implement invertible logic has emerged as a potential solution, with the primary challenges being the realization of high-quality random sources and efficient circuit mapping schemes. In this work, we propose a reliable design for invertible logic circuits based on stochastic spin-transfer torque magnetic tunnel junctions (MTJs) and validate it through SPICE simulations. To achieve this, we develop a physics-driven stochastic MTJ model using Verilog-A, which is then implemented to construct binary stochastic neurons for building restricted Boltzmann machines (RBMs). Using linear programming (LP), the stochastic MTJs are weighted and interconnected to construct elementary RBM-based invertible logic gates, including AND, OR, NOT, and NAND gates. Furthermore, through logic synthesis, invertible logic circuits capable of realizing arbitrary logic functions are achieved. RBMs whose weights are determined by LP not only eliminate the need for training but also enhance iteration speed. Finally, we demonstrate how to solve the Boolean satisfiability problem using the proposed invertible logic circuits. Power consumption and area estimations indicate that our design consumes fewer resources compared to pure CMOS implementations.