Fast Correction Method for Thermal Network Models of Multi‐Chip Parallel Power Modules

ABSTRACT To precisely obtain the chip junction temperature in multi‐chip, parallel power modules, a thermal network model that incorporates transverse thermal diffusion and thermal coupling is to be established. The conventional thermal network model, built using the thermal diffusion angle, offers the advantages of simplicity and high computational speed. However, the conventional thermal network model exhibits a large computational error when the effective convective heat transfer area cannot be equivalent to a complete circle, necessitating enhancements to the thermal network model. First, materials of each layer in the thermal network model are theoretically modeled in this paper, followed by an analysis of the root causes of errors in the conventional model. Second, a fast correction method is introduced for the equivalent thermal network model of the power module. The method rectifies the thermal network model of a chip whose effective convective heat transfer area exceeds the edge of the heat sink substrate by substituting it with the corresponding value from the thermal network model of an adjacent chip. The calculation accuracy of the thermal network model is significantly improved postcorrection. Finally, a buck experimental platform has been constructed, and the effectiveness of the proposed correction method has been validated experimentally.