Design of Power efficient Approximate Multiplier

Approximate computing in Arithmetic Logic Unit design place a vital role in low power design in signal and image processing applications by introducing accuracy as a performance metric. This study proposes a 16-bit multiplier design that only takes into account the carry generated by the output’s first 16 Most Significant Bits. This proposed architecture design reduces area, power and increase % error of the output which is tolerable in high performance system design. The suggested multiplier architecture applied to image compression application using Discrete Cosine Transform and the simulation results are quantified, which uses less power and occupies less space than existed multiplier architectures. Proposed approximate multiplier architecture offers 67.62% power reduction at a PSNR of 22.19 dB.