Understanding the Mechanism of Metal Oxide Defect Formation at the Via Bottom

The semiconductor manufacturing process is a complex and intricate system that is susceptible to even the slightest deviations. Yield issues can significantly affect production efficiency and product reliability. Therefore, a comprehensive understanding of the intertwined technical and systemic factors involved is essential for maintaining high yield rates in semiconductor manufacturing. This paper presents an in-depth analysis of a recurring yield issue, illustrating how various factors can converge to compromise yield for the borderless or zero enclosure Via* design. The proposed yield loss mechanism, a key contribution of this analysis, was validated, paving the way for its practical application in selecting wet cleaning chemicals for the post Via* etch residual removal for tight Via* overlay designs.