Next-generation ECC processor on FPGA: Leveraging Koblitz curves for enhanced performance

This paper presents a hardware design of an Elliptic Curve Cryptography (ECC) processor optimized for Field Programmable Gate Arrays (FPGAs), focusing on the Koblitz curve Secp256k1. We introduce a novel, constant-time ECC processor design that efficiently performs Elliptic Curve Point Multiplications (ECPM). The design features an optimized Arithmetic Unit and a dual parallel-structured instruction set architecture that reduces computation time and minimizes hardware resource demands by utilizing Brent-Kung adders. Implemented on the Xilinx FPGA Kintex-7 for the Secp256k1 curve, the architecture operates at 202.3 MHz, utilizing 16.2k slices and 54 DSP blocks. This work aims to enhance ECC processors' performance and resource efficiency while preserving flexibility for secure digital applications in environments with limited computing resources.

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Publication Details

Journal
Ain Shams Engineering Journal
Published
2025-05-27
DOI
https://doi.org/10.1016/j.asej.2025.103495
Citations
1
Primary Topic
Cryptography and Residue Arithmetic
Type
article
Field-Weighted Citation Impact
3.25
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article

Next-generation ECC processor on FPGA: Leveraging Koblitz curves for enhanced performance

Hung K. Nguyen, Linh Tran, Tung Lam Nguyen, Khai Nguyen et al.
1 citations
Ain Shams Engineering Journal
Cryptography and Residue Arithmetic
3.25
article

Next-generation ECC processor on FPGA: Leveraging Koblitz curves for enhanced performance

Hung K. Nguyen, Linh Tran, Tung Lam Nguyen, Khai Nguyen, Vy Nguyen
article en
1 citations

Abstract

This paper presents a hardware design of an Elliptic Curve Cryptography (ECC) processor optimized for Field Programmable Gate Arrays (FPGAs), focusing on the Koblitz curve Secp256k1. We introduce a novel, constant-time ECC processor design that efficiently performs Elliptic Curve Point Multiplications (ECPM). The design features an optimized Arithmetic Unit and a dual parallel-structured instruction set architecture that reduces computation time and minimizes hardware resource demands by utilizing Brent-Kung adders. Implemented on the Xilinx FPGA Kintex-7 for the Secp256k1 curve, the architecture operates at 202.3 MHz, utilizing 16.2k slices and 54 DSP blocks. This work aims to enhance ECC processors' performance and resource efficiency while preserving flexibility for secure digital applications in environments with limited computing resources.

Ain Shams Engineering JournalVol. 16(9)
Vietnam National University Ho Chi Minh City (VN), Ho Chi Minh City University of Technology (VN)
Affordable and clean energy
Openalex Percentile: Top 9%
Cryptography and Residue Arithmetic
3.25
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