Device Optimization to Enable Ultra Low Leakage Logic FinFETs

Leakage reduction is a key consideration for modern chip design as transistors continue to shrink in size to improve power efficiency in integrated circuits. In this paper, we present techniques used to develop ultra-low leakage (ULL) logic FET and SRAM on GlobalFoundries 12LP+ CMOS technology. We will show how junction and gate engineering can lead to ~11x/7x reduction in NFET/PFET devices leakage by keeping the technology on the ring oscillator (RO) performance trend. We will also present more than 10x decrease in static random-access memory (SRAM) leakage during data-retention mode with no degradation on threshold voltage mismatch.