An Effective Method to Compensate for Testing Induced SBFET Degradation by Charging Deep-Level Interface Trap
In this paper, the threshold voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>th</sub></i>) of Schottky barrier field effect transistors (SBFETs) based on ultra-thin silicon on insulator (SOI) wafer shift induced by electrical test is analyzed. Repeated testing gives rise to a positive shift of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>th</sub></i> which is similar to the constant voltage stress effect found in two-dimensional material. The series resistance of Source and Drain (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R<sub>sd</sub></i>), mobility (μ), and trapped charge are studied. The positive Δ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>th</sub></i> is independent of the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R<sub>sd</sub></i> and μ, but related to the deep-level acceptor interface trap which is charged during test. The main reason for trap charging is that the Source and Drain contact prepared by metal deposition cannot provide electrons for trap capturing before testing. In order to compensate the Δ<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V<sub>th</sub></i> induced by test, a deep-level trap charging method is proposed. The necessity of this new test method is verified by irradiation experiments.
Authors
- Yuyang Ding (ORCID: https://orcid.org/0000-0002-1127-6278)
- Tianchun Ye (ORCID: https://orcid.org/0000-0002-2384-9037)
- Bo Li (ORCID: https://orcid.org/0000-0003-4905-2744)
- Lei Shu (ORCID: https://orcid.org/0000-0002-5688-1447)
- Yong Xu (ORCID: https://orcid.org/0000-0002-6800-234X)
- Fanyu Liu (ORCID: https://orcid.org/0000-0002-6154-4971)
- Yuchong Wang (ORCID: https://orcid.org/0000-0002-8040-5491)
- Zhengsheng Han (ORCID: https://orcid.org/0000-0003-2087-0356)
- Tiexin Zhang (ORCID: https://orcid.org/0000-0001-6752-0818)
- Siyuan Chen (ORCID: https://orcid.org/0000-0003-3402-6236)
- Shi Li (ORCID: https://orcid.org/0000-0001-9140-9415)
- Jing Wan (ORCID: https://orcid.org/0000-0002-6339-4006)
- Yuchen Wu (ORCID: https://orcid.org/0009-0002-5592-9960)
Institutions
- Chinese Academy of Sciences (CN)
- Fudan University (CN)
- Nanjing University of Posts and Telecommunications (CN)
- Institute of Microelectronics (SG)
- China Institute of Atomic Energy (CN)
- Institute of Microelectronics (CN)
- Shanghai Fudan Microelectronics (China) (CN)
- National Institute of Metrology (CN)
Publication Details
- Journal
- IEEE Access
- Published
- 2025-01-01
- DOI
- https://doi.org/10.1109/access.2025.3573406
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China
- National Key Research and Development Program of China