A Fast-Transient One-Shot Droop Recovery Digital LDO With Reinforcement-Learning Droop Compensation for D2D Interfaces

This letter presents a digital low-dropout regulator (DLDO) featuring a one-shot voltage droop recovery and an ultrafast settling time of 8 ns, achieved through reinforcement-learning-based self-adaptive compensation (RL-SAC). The RL-SAC performs real-time background learning to identify the optimal current required to compensate for a given voltage droop. By iteratively learning the voltage droop, the RL-SAC enables the one-shot droop recovery, ensuring instant stabilization of the output voltage. A prototype was fabricated in a 40 nm CMOS process with an on-chip output capacitor of 100 pF. The prototype supports an input voltage V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> range from 0.4 to 0.9 V. Measurement results demonstrated a droop settling time of 8 ns and a voltage droop of 145 mV against a load current step of 102 mA/ns at V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> of 0.8 V and V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> of 0.75 V.