Process Challenges attributing to Lithography Overlay Misalignment : A Case Study on BEOL Lithography Process

Photolithography is one of the most complex and critical processes in semiconductor wafer fabrication. It plays a key role in achieving high resolution, high photoresist sensitivity, minimal feature sizes, precise process control, and low defect density.[1] As technology continues to shrink, yield improvement has become a major challenge in wafer fabrication. In particular, edge die yield loss remains a critical issue in semiconductor manufacturing. Within the lithography process, this yield loss is often caused by pattern uniformity issues, pattern distortion, resist lifting, and defocus.[1] To monitor wafer performance and predict yield, methods such as Statistical Process Control (SPC) and Advanced Process Control (APC) are widely used. However, yield loss can still happen even when all inline monitor reports values within specification limits.This study examines a case study in the Back-End-of-Line (BEOL) lithography process, where significant yield loss occurred despite Overlay and critical dimension (CD) measurements being within specification limits. The primary cause was a misalignment between the via and metal-metal layers, exacerbated by slightly larger via CD and a sloped upstream metal profile at wafer edge. As a result, vias landed improperly on the metal, particularly in line-on-line structures on the wafer edge, leading to yield loss, causing circuit short or reliability concern.This study highlights the need for enhanced monitoring techniques and process control strategies to mitigate variations and improve overall yield in semiconductor manufacturing. This paper also proposes a new inline monitor method to combine the upstream and downstream factors and automatically trigger mask rework to predict yield loss.