Void Defect Improvement with Barrier Metal-Cu Seed and Electroplating Recipes Optimization

Semiconductor back end of line metallization requires successful integration of barrier metal (BM), copper seed, and copper electroplating, among other processes, in order to carry signals and power to the transistors below. This can be impeded or blocked by voids in the metal lines. This paper reports an investigation into the reduction of voids on a particular high aspect ratio feature through the optimization of the interface barrier metal (BM), copper seed, and copper electroplating conditions. Results show that these optimizations significantly reduced the void count and allowed for a reduced overall resistance of the metal layer, contributing to an increase in wafer yield.