Elimination of 3D NAND Through-Array Contact Shortage on Yield Enhancement

In the development of a complementary metal-oxide-semiconductor (CMOS) under array (CuA) structured 3D NAND memory, the through-array contact (TAC) process plays a critical and indispensable role in the operation of such devices. In this work, during the preliminary wafer acceptance test (WAT), a circuit short issue corresponding to TAC module along with significant yield loss is reported. Failure analysis reveals that abnormal leakage is caused by the insufficient isolation between the bottom of the TAC and the neighboring poly-silicon grounding layers. More detail analyses by physical profiles and the X-ray metrology technique indicate that it might be directly relate to the tilting behavior of patterning TAC in plasma etching. A promising solution to improve the plasma tilting behavior in etching is demonstrated and that managed to recover the product yield effectively.