A Novel Method to Optimize Asymmetric NMOS Device Performance without Impacting the Main Device Functionality

The continuous drive for scaling and its associated challenges like short channel effects on one hand, the quest for high drive current and requirements of high voltage applications on other hand, give rise to newer device architecture like asymmetric LDD NMOS devices. When both the main device and the asymmetric slave devices are present on same integrated circuit, independent process tuning for each device is not normally possible as they share same set of masks and process steps. In this paper, we studied the sensitivity of each process to main and asymmetric devices, and we propose, for the first time, a methodology to independently adjust the asymmetric NMOS device performance without impacting the main devices. By inserting a N<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>H<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> plasma surface treatment after the LDD/pocket implant, the behavior of asymmetric NMOS can be modified with little effect on standard NMOS. The N<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>H<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> treatment after the LDD implant believed to alter the dopant profile near to the pocket region and determines the threshold voltage. No electrical or reliability degradation is observed with the introduction of forming gas treatment. No such study was published before and the study from this paper provides new degree of freedom to process engineers to optimize the processes to achieve both main and asymmetric device specification requirements.