Radiation-Hardened—AI-Accelerated Custom IC Design Methodology

In this work, a radiation hardened - AI accelerated custom IC design methodology is proposed. The methodology employs reinforcement learning (RL) to optimize the IC design process, integrating radiation dosage performance degradation assessments and radiation-hardened-by-design (RHBD) MOSFET cell implementations at both schematic and layout levels. This approach streamlines the development of radiation-immune silicon products by embedding artificial intelligence to accelerate the design process and advanced radiation hardening strategies directly into the standard design flow. To validate the proposed framework, a charge-sensitive amplifier (CSA) based on a folded-cascode architecture is designed and assessed in a 180 nm standard CMOS process, demonstrating the efficiency of the methodology in radiation-resilient analog front-end systems.

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Publication Details

Journal
IEEE Access
Published
2025-01-01
DOI
https://doi.org/10.1109/access.2025.3574058
Citations
1
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
Field-Weighted Citation Impact
0.73
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article

Radiation-Hardened—AI-Accelerated Custom IC Design Methodology

S. Karipidis, Vasiliki Gogolou, T. Noulis, E. Papageorgiou et al.
1 citations
IEEE Access
Integrated Circuits and Semiconductor Failure Analysis
0.73
article

Radiation-Hardened—AI-Accelerated Custom IC Design Methodology

S. Karipidis, Vasiliki Gogolou, T. Noulis, E. Papageorgiou, Anastasios Michailidis
article en
1 citations

Abstract

In this work, a radiation hardened - AI accelerated custom IC design methodology is proposed. The methodology employs reinforcement learning (RL) to optimize the IC design process, integrating radiation dosage performance degradation assessments and radiation-hardened-by-design (RHBD) MOSFET cell implementations at both schematic and layout levels. This approach streamlines the development of radiation-immune silicon products by embedding artificial intelligence to accelerate the design process and advanced radiation hardening strategies directly into the standard design flow. To validate the proposed framework, a charge-sensitive amplifier (CSA) based on a folded-cascode architecture is designed and assessed in a 180 nm standard CMOS process, demonstrating the efficiency of the methodology in radiation-resilient analog front-end systems.

IEEE AccessVol. 13
Aristotle University of Thessaloniki (GR)
Openalex Percentile: Top 28%
Integrated Circuits and Semiconductor Failure Analysis
0.73
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Radiation-Hardened—AI-Accelerated Custom IC Design Methodology — S. Karipidis, Vasiliki Gogolou, et al. · IEEE Access (2025) | TGRS Research Map | TGRS