Enhanced Annealing and Material with Crystal Originated Particles for Localized Yield Improvement

High temperature annealing is widely applied to repair implantation damage in high voltage Bipolar-CMOS-DMOS (BCD) devices. However, the boat pin contact region often experiences plastic deformation under such aggressive thermal conditions. In this paper, we demonstrate an optimized furnace annealing process designed to enhance Bulk Microdefects (BMDs) formation, combined with Crystal Originated Particles (COPs) in the silicon substrate, to improve the wafer mechanical strength. The optimized condition achieves a 90% reduction of 4-pin defect depth, significantly minimizing wafer deformation and enhancing yield performance.