Coplanar High‐Speed and Efficient Multiplier Design for QCA Technology

With the continuous expansion of the digital domain and the increasing need for higher chip integration, quantum‐dot cellular automata (QCA) has emerged as a promising alternative to CMOS technology. However, existing QCA designs often face significant challenges, including high delay, large area, and inefficient wire crossing techniques, which limit their practical applicability. This paper addresses these gaps by proposing novel two‐bit and four‐bit multiplier designs that leverage efficient adder blocks and innovative coplanar wire crossing strategies. Our work introduces eight key design guidelines derived through extensive simulation and experimentation in the QCADesigner. These guidelines address critical challenges in the QCA circuit design, such as signal propagation, clocking, and interference minimization, ensuring reliable logic transmission and improved circuit performance. The proposed single‐layer multipliers demonstrate significant improvements over existing designs, with a 65% reduction in delay, a 43% reduction in area, and a 39% reduction in cell count for the two‐bit multiplier. For the four‐bit multiplier, improvements of 32.5% in delay, 48% in area, and 28% in cell count are achieved. In comparison with multilayer designs, our two‐bit multiplier achieves similar delay performance while offering 16% and 31% improvements in area and cell count, respectively. Although the four‐bit multiplier shows an increase in area, cell count, and delay compared to multilayer designs, it remains the most efficient single‐layer implementation to date. The proposed designs not only advance the state‐of‐the‐art in QCA multipliers but also provide a scalable framework for future research in high‐speed, low‐power digital circuits. This work highlights the importance of systematic design methodologies in QCA technology and paves the way for more efficient and reliable nanoscale computing systems.