A Method for Accurate Settling Performance Design of SC Integrators Employing Two‐Stage OTAs

ABSTRACT Conventional methods for the settling performance design of switched‐capacitor integrators are only applicable under the assumption of an ideal feedback loop model of the embedded operational transconductance amplifiers, and the design results obtained are inaccurate. An approach for the accurate design of switched‐capacitor integrators employing two‐stage amplifiers is presented in this paper. The settling time expression is first derived based on an effective settling behavior model of integrators, and a design procedure aimed at a given settling time is then developed. The design accuracy is achieved by the error compensation for the analytical model estimated from the output of the SPICE simulation and the iteration of the design procedure. All error sources incurred by various parasitic effects in the circuit, including those of the switch transistors, can be considered, and design results are attained with SPICE‐level precision. Simulated design examples of two switched‐capacitor integrators are provided to verify the accuracy and effectiveness of the method.