High-Reliability IoT SRAM Architecture Using Nwise and Pwise Cells for Space Applications

SRAM cells play a critical role in memory components such as caches, register files, and translation lookaside buffers, with their design needing to meet specific requirements based on their intended use. In the aerospace sector, where power efficiency and reliability are paramount due to constrained power resources and exposure to high radiation, the Nwise cell, designed with 28nm FD-SOI technology, addresses these challenges by providing strong reliability and resistance to radiation. This research also presents the Pwise cell, a novel design derived from the Nwise cell and utilizing the same 28nm FD-SOI technology. Simulations indicate that both the Nwise and Pwise cells offer excellent protection against single-event upsets (SEUs) and multiple-event upsets (MEUs) in space environments. The Pwise cell, with its lower read and write latencies, is well-suited for log file applications, while the Nwise cell, with lower read latency and reduced power consumption, is ideal for cache memory designs. Both cells present promising options for space-grade memory systems.

Publication Details

Journal
Journal on Electronic and Automation Engineering
Published
2025-05-26
DOI
https://doi.org/10.46632/jeae/4/2/27
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
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article

High-Reliability IoT SRAM Architecture Using Nwise and Pwise Cells for Space Applications

Journal on Electronic and Automation Engineering
VLSI and Analog Circuit Testing
article

High-Reliability IoT SRAM Architecture Using Nwise and Pwise Cells for Space Applications

article en

Abstract

SRAM cells play a critical role in memory components such as caches, register files, and translation lookaside buffers, with their design needing to meet specific requirements based on their intended use. In the aerospace sector, where power efficiency and reliability are paramount due to constrained power resources and exposure to high radiation, the Nwise cell, designed with 28nm FD-SOI technology, addresses these challenges by providing strong reliability and resistance to radiation. This research also presents the Pwise cell, a novel design derived from the Nwise cell and utilizing the same 28nm FD-SOI technology. Simulations indicate that both the Nwise and Pwise cells offer excellent protection against single-event upsets (SEUs) and multiple-event upsets (MEUs) in space environments. The Pwise cell, with its lower read and write latencies, is well-suited for log file applications, while the Nwise cell, with lower read latency and reduced power consumption, is ideal for cache memory designs. Both cells present promising options for space-grade memory systems.

Journal on Electronic and Automation EngineeringVol. 4(2 June 2025)
Openalex Percentile: Top 90%
VLSI and Analog Circuit Testing
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