SWSS-FS: An Enhanced Sunway Full-System Architecture Simulator

Architecture simulators serve as an important tool for modeling and simulating processor microarchitectures, particularly in the design and verification of Sunway processors. Full-system simulation is more accurate and user-friendly, and it is often used for architectural simulation, making its implementation more complex. However, SWSS (Sunway SuperScalar Simulator) is a user-mode architecture simulator that does not support full-system simulation. The research in this paper extends SWSS to implement multi-core functionality simulation and architectural simulation. It proposes a hybrid full-system architecture simulation technology and a Client-Server-based full-system simulation interaction technology leveraging shared memory, resulting in the construction of the Sunway full-system architecture simulator SWSS-FS. The aim is to enhance the accuracy and usability of Sunway architecture simulators. SWSS-FS achieves an average IPC error of less than 8% compared to the simulated target chip in SPEC2006 benchmark tests, making it more accurate than user-mode simulation. In the SPLASH2 parallel benchmark tests, the error is within 10% compared to the simulated target chip. It plays an important role in exploring instruction set design, analyzing program performance bottlenecks, and correctness verification, thereby advancing the design and verification of Sunway processors.