A Novel Adaptive Fitting and Trimming Algorithm of Chip Power Module Based on WaferLevel Packaging

Affected by the integrated circuit manufacturing process, the output of the power module inside the chip will have a certain degree of deviation. These deviations need to be calibrated through trimming tests using ATE (Auto Test Equipment). Due to the increase in the number of trimming modules inside the chip, the trimming test items occupy increasing test time, and test costs are also rising. Most previous research reduces the test time by sacrificing the precision of trimming, which makes it difficult to achieve the balance between the test time and the test accuracy. Although the single test time is reduced, the impact of test accuracy on yield is ignored. This paper conducts trimming tests on the power module of the wafer-level packaged chip and proposes an adaptive fitting trimming algorithm. The algorithm uses the trimming direction and trimming bit factors, and then calculates the optimal trim code through the fitted curve. The curve is fitted independently for each chip, which can effectively improve the test accuracy. Through process window skew verification and comparison with traditional algorithms, it is proved that the yield after trimming optimization can be increased by more than 1%. For the worst process conditions, the yield can even be increased by 20%. At the end of the paper, 500 mass-produced wafers were tested by the built ATE with the adaptive fitting trimming algorithm. The test data showed that the optimized voltage output accuracy can reach 98%, the current output accuracy can reach 99% and the test cost can be saved by 62.25%, which proves that the adaptive fitting trimming algorithm can effectively reduce the test time while the trimming accuracy can be improved.