A Low-Power Partial-Prediction SAR ADC With Feedback Resistor-Assisted Adaptive FIA

This brief introduces a low-power, non-reset, partial predictive successive approximation register (SAR) analog-to-digital converter (ADC) designed for portable applications. The architecture quantizes the higher 7-bit digital codes using 6 bitwise capacitors without requiring resetting. Additionally, a feedback resistor-assisted adaptive floating inverter amplifier (AFIA) is proposed to optimize comparator’s power consumption. The prototype, occupying 0.067 mm2, was fabricated using a 0.13 lm standard CMOS process with a supply voltage of 1.2/1 V. Measurement results show that the ADC achieves an effective number of bits (ENOB) of 9.31 and a spur-free dynamic range (SFDR) of 72 dB at a 10 kHz sample rate with a Nyquist sinusoidal input. Furthermore, the ADC demonstrates a figure of merit (FoM) of 9.6 fJ/conversion step with a 60 Hz sinusoidal input, consuming a total power of 80 nW. Proposed AFIA contributes only 19% to the total power consumption.