Impact of asymmetric source-to-gate and drain-to-gate overlap lengths on the performance of back gate IGZO TFTs

Abstract In this article, an asymmetric In–Ga–Zn–O (IGZO) thin-film transistor structure with an extended source-to-gate overlap length ( L S ) and shortened drain-to-gate overlap length ( L D ) is proposed. The asymmetric overlap length structure( L S = 0.9 μm, L D = 0.1 μm) achieves a 75.04% reduction in off-state current ( I off ), a 17.67% increase in on-state current ( I on ), and a 4.6 x enhancement in I on / I off compared to the conventional symmetric overlap structure ( L S = 0.5 μm, L D = 0.5 μm). It accomplishes these improvements without requiring additional processing or increasing the thermal budget. The study reveals that with a constant L S , reducing the L D from 1.5 to 0.1 μm reduces I off by 87.47%. Conversely, with a constant L D , reducing L S from 1.5 to 0.1 μm decreases the I on by 64.54%. These results demonstrate that L S and L D exert distinct and opposite influences on I on and I off . Furthermore, simulations examine the dependence of I on and I off on L S and L D under various source/drain workfunction. This work provides guidance for device optimization in future 3D DRAM applications.