Voltage Regulation of Data Strobe Inputs in Mobile Dynamic Random Access Memory to Prevent Unintended Activations

In mobile dynamic random access memory (DRAM) receivers, the data strobe complement (DQS_c) and data strobe true (DQS_t) signals must be maintained at high and low voltage levels in the write data strobe off (WDQS_OFF) mode. Therefore, we developed a voltage regulation circuit to optimize the differential voltage signals of DQS_c and DQS_t, ensuring a high voltage level above 0.9 V and a low voltage level below 0.3 V. Experimental results showed that the circuit stably maintained DQS_c above 0.9 V and DQS_t below 0.3 V before the write preamble time (tWPRE) and in WDQS_OFF mode. This configuration effectively prevents unintended activation in the mobile DRAM DQS input receiver.