Heterogeneous Capacitor‐less Two‐transistor Dynamic Random Access Memory Cell with Long Retention Time and High Sensing Current Supporting 5‐Bit Multilevel Operation

A heterogeneous capacitor‐less two‐transistor (2T0C) dynamic random access memory (DRAM) cell is fabricated, featuring a write transistor with an amorphous indium–gallium–zinc–oxide (a‐IGZO) channel and a read transistor with a single crystal silicon (Si) channel. These transistors are vertically integrated to achieve high integration density. A data retention time of over 4800 s is achieved due to the wide bandgap of a‐IGZO, and a high sensing current of over 166 μA μm −1 is achieved due to the high mobility of the Si. This high sensing current allows for a short read latency of 1.34 ns and 5‐bit multilevel cell operation, the highest reported for 2T0C DRAM cells.