Survey of Verification of RISC-V Processors

Abstract This paper is a survey of the various verification methods available for RISC based processors. The RISC-V processors are open standard that can have user-based extensions. This makes their verification complex and prone to errors. There is ongoing research in this area. This paper illustrates the criteria for deciding a Verification Plan while considering various available verification methods, verification time, and software costs. Several hardware design verification approaches from Formal Verification to Simulation based, Fully Automated Verification Plan to Security and Trojans are discussed. A Comparison between features and verification methods employed for Intel, ARM and RISC based processors is also done. The current RISC-V hardware design verification methods in use like self-checking tests, testbench use of standards, virtual verification peripherals and many more along with the required software and tools are described. In depth analysis of previous and current research on various available and newly developed RISC-V processors is chronicled with their code coverage, functional coverage, limitations and bug detection details.