Time‐Domain ADPLL BPSK, QPSK, and 8PSK Demodulators

Time‐domain all‐digital‐phase‐locked‐loop phase‐shift‐keying (PSK) demodulators are proposed for BPSK, QPSK, and 8PSK signals. The demodulator architectures are highly suitable for low‐voltage nanoscale CMOS techology. Data‐bit extraction as well as phase control for loop locking can be effectively achieved in a time domain with simple logic operators such as positive‐edge‐trigger RESET/SET (pRSFF) and delay flip flops (DFF). Pulse width of the phase‐control signal is sampled and passed on to the digitally‐controlled oscillator (DCO) for frequency and phase adjustment. Two different phase control methods have been employed to appropriately alter a duty cycle of the phase‐control signal. The first option is performed by multiplexing a single‐phase DCO signal as selected by the extracted data bits. The second technique uses m DCO phases simultaneously for phase‐control detection with the incoming m ‐PSK signal. This helps reduce the intertwined loop of the first method to a single‐loop structure. This modular BPSK, QPSK, and 8PSK demodulation concept has been successfully verified by measurement with discrete components at a carrier frequency of 100 kHz operating under a 5‐V supply.