Compactly Hardware Implementation of a High-Speed Activation Function Based on Phase-Change Memory in Neural Network

Activation function (AF) is a pivotal yet resource-intensive component in artificial neural network (ANN) hardware implementations. Digital AFs offer high accuracy but require data conversions incurring hardware overhead in analog-memory-based ANNs, making analog AFs more suitable. However, existing analog approaches leveraging device physics for direct AF implementations face significant challenges in integration and scalability, underscoring the urgent need to explore alternative memory devices for more compact and reliable AF implementations. This work proposes a low-power, high speed AF constructed directly using the inherent Sinh current-to-voltage (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i>–<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i>) characteristics of phase-change memory (PCM) devices. We designed an analog circuit to implement the inverse hyperbolic sine (Arsinh) function and achieved the target AF through the rapid read operation of a single PCM cell. Experimental results demonstrate that the proposed Arsinh function exhibits a low root-mean-square error (RMSE) compared to the ideal Arsinh function, with a highly efficient operational power consumption ranging from ~0.17 nW to 3.5 μW. Additionally, the delay time (~70 ns) is comparable to the speed of matrix–vector multiplications (MVMs) in mature System-on-Chip (SoC) implementations. Furthermore, the AF achieved a classification accuracy of 94.81% on the MNIST dataset and 91.01% on the Fashion MNIST dataset, confirming its effectiveness and applicability in practical scenarios.