Energy-Optimized High - Performance Ternary Adders based on CNTFET Technology

This research will focus on building high performance and energy-efficient ternary logic circuits with CNTFET technology. The proposed work will provide a detailed optimization of some important parameters such as energy consumption, propagation delay, and performance of the viable circuits based on the primitive ternary gates, i.e., inverters, NAND, NOR, and XOR. Take active characteristics of CNTFETs that allow in the range of threshold voltages by varying diameters of the carbon nanotube, and apply these designs to ameliorate the speed and power efficiency performance of the traditional ternary circuits based on MOSFETs. With those achievements, more simulations are conducted using Cadence Virtuoso with CNTFET models and related comparisons between CNTFET-based designs versus conventional CMOS circuits are made, as well as scalability analysis towards much more complex digital applications, including ternary adders and multipliers. Results will further solidify CNTFETs as the next interesting alternative for multi-valued logic systems by allowing next-generation electronics to fit ever more devices into compact, power efficient, and high-speed solutions.