Finite Element Analysis of the Asymmetric Warpage Induced by the Oxidation Process in Trench Insulated Gate Bipolar Transistor (Trench IGBT) 12” Si Patterned Wafers

Trench Insulated Gate Bipolar Transistors (IGBTs) represent a significant advancement in power semiconductor technology, offering notable improvements over traditional planar IGBTs. Despite these advancements, asymmetric wafer warpage remains a critical challenge due to the complex structure and high-stress processes involved from the early stages of fabrication. The oxidation process, essential for gate formation in trench IGBT fabrication, plays a pivotal role in inducing asymmetric warpage due to thermal stress, intrisic stress, volume expansion, and non-uniform oxidation. Accurate prediction and management of this warpage are crucial for enhancing yield and performance in manufacturing. Finite Element Analysis (FEA) is a valuable tool for predicting and managing warpage in semiconductor manufacturing. In this study, we employed two commercial simulation software packages, COMSOL and ANSYS, to investigate the emergence of asymmetric warpage in trench IGBTs resulting from the gate-formation oxidation step. Initially, 3D-CAD models of the oxidized micron trench structure were designed on a silicon (100) substrate using both COMSOL and ANSYS. Our results indicate that, by carefully selecting the thermomechanical properties of the hundred nm-size silicon oxide layer covering the micron-sized silicon trenches, it is possible to accurately reproduce the asymmetric warpage induced by the oxidation step in the two principal perpendicular directions. To further validate our findings, we compared them with experimental results at the 300 mm wafer scale by employing an independent homogenization method. Using ANSYS Material Designer, we determined a homogenized layer of the trench-patterned oxidized structure. Also in this case, by carefully selecting the thermomechanical properties of the materials, we successfully replicated the asymmetric warpage at wafer level. These findings can be of help in predicting the behaviour of newly designed trench structures and mitigating their asymmetric warpage.

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Published
2025-04-06
DOI
https://doi.org/10.1109/eurosime65125.2025.11006629
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1
Primary Topic
Thin-Film Transistor Technologies
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article
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article

Finite Element Analysis of the Asymmetric Warpage Induced by the Oxidation Process in Trench Insulated Gate Bipolar Transistor (Trench IGBT) 12” Si Patterned Wafers

Giuseppe Luigi Malgioglio, Mohamed Boutaleb, Marco Renna, Vincenzo Vinciguerra et al.
1 citations
Thin-Film Transistor Technologies
0.73
article

Finite Element Analysis of the Asymmetric Warpage Induced by the Oxidation Process in Trench Insulated Gate Bipolar Transistor (Trench IGBT) 12” Si Patterned Wafers

Giuseppe Luigi Malgioglio, Mohamed Boutaleb, Marco Renna, Vincenzo Vinciguerra, Fabrice Roqueta, P. Zuliani, Andrea Li Bassi, Davide Fagiani, Simone Dario Mariani, F. Sabatini
article en
1 citations

Abstract

Trench Insulated Gate Bipolar Transistors (IGBTs) represent a significant advancement in power semiconductor technology, offering notable improvements over traditional planar IGBTs. Despite these advancements, asymmetric wafer warpage remains a critical challenge due to the complex structure and high-stress processes involved from the early stages of fabrication. The oxidation process, essential for gate formation in trench IGBT fabrication, plays a pivotal role in inducing asymmetric warpage due to thermal stress, intrisic stress, volume expansion, and non-uniform oxidation. Accurate prediction and management of this warpage are crucial for enhancing yield and performance in manufacturing. Finite Element Analysis (FEA) is a valuable tool for predicting and managing warpage in semiconductor manufacturing. In this study, we employed two commercial simulation software packages, COMSOL and ANSYS, to investigate the emergence of asymmetric warpage in trench IGBTs resulting from the gate-formation oxidation step. Initially, 3D-CAD models of the oxidized micron trench structure were designed on a silicon (100) substrate using both COMSOL and ANSYS. Our results indicate that, by carefully selecting the thermomechanical properties of the hundred nm-size silicon oxide layer covering the micron-sized silicon trenches, it is possible to accurately reproduce the asymmetric warpage induced by the oxidation step in the two principal perpendicular directions. To further validate our findings, we compared them with experimental results at the 300 mm wafer scale by employing an independent homogenization method. Using ANSYS Material Designer, we determined a homogenized layer of the trench-patterned oxidized structure. Also in this case, by carefully selecting the thermomechanical properties of the materials, we successfully replicated the asymmetric warpage at wafer level. These findings can be of help in predicting the behaviour of newly designed trench structures and mitigating their asymmetric warpage.

STMicroelectronics (France) (FR), Politecnico di Milano (IT)
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Thin-Film Transistor Technologies
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