Implementation and Evaluation of AES on Virtex-7 FPGA

The Advanced Encryption Standard is a widely used symmetric block cipher that encrypts and decrypts data to ensure security using 128, 192, 256 bit keys. This study optimises the implementation of this algorithm using 128 bit key on a Xilinx Virtex 7 FPGA, ensuring high hardware efficiency and speed. Using an iterative design approach, the system decreases hardware complexity while retaining speed. The implementation is written in Verilog and synthesised in Xilinx Vivado, with performance metrics including power consumption, resource utilisation, and processing speed.