Performance Evaluation of Standard Ternary Inverters Using Carbon Nanotube Field Effect Transistors

Ternary logic system can transfer more data as compare to binary logic in a digital system. This paper presents performance analysis of various existing energy-efficient designs for standard ternary Inverter (STI) logic gates. The circuits of various STIs have been designed using CNTFET technology. Simulations have been performed using the Synopsys HSPICE tool with a 32 nm CNTFET model, provided by Stanford University. Average power consumption and propagation delays have been calculated for each design, and values of PDP have been computed.