Reduced-Order Modelling for Efficient Chip-Package-Board Design

In the development cycle of microelectronic components and systems, comprehensive reliability assessments of the products in the virtual environment save the costs of manufacturing prototypes. In this simulation process, component manufacturers need to share component models with other partners along the value chain while at the same time safeguarding their intellectual property. Therefore, in this work, model order reduction methods are implemented to generate highly accurate compact models, which hide the details of the product, such as material properties and geometry. For system manufacturers, that integrate different components on a printed circuit board, these compact models can be re-integrated into their models for virtual reliability tests via the superelement techniques.