Finite Element Analysis of Warpage Hysteresis Loop Evolution and Bifurcation in Thinned 4H-SiC Cu_ECD Metalized Wafers

The thinning of large wafers often leads to increased warpage due to residual stress, adversely affecting wafer processability and chip-to-package interaction (CPI). Mitigating wafer warpage, particularly preventing its progression to critical phenomena such as bifurcation or buckling, is crucial in the manufacturing also of large wide-bandgap semiconductor wafers of 4H-SiC. This study advances the investigation of the warpage hysteresis loop (WHL) evolution by examining the progression towards bifurcation in highly stressed layers, specifically focusing on electrochemically deposited copper (Cu_ECD) on thinned 4H-SiC (0001) wafers. Exploiting ANSYS finite element analysis (FEA), the research considers the asymmetries of bifurcation in <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{Si}(001)$</tex> and SiC (0001) wafers during the thinning process. The study provides a comparative analysis of the WHL evolution in Si (001) wafers versus 4H-SiC (0001) wafers, offering insights into the distinct behaviors of these materials under stress.