Enhanced Retention Characteristics of Subthreshold Hf-ZnO Synaptic Pass-Transistors with Ultralow Power Consumption

An analysis on the retention characteristics of an ultralow power synaptic pass-transistor (SPT) with a Hf-ZnO channel layer is presented for both higher intelligence and longer-term memory of the neuromorphic system. The SPT consists of the synaptic thin-film transistor (TFT) and load TFT, employing the pass-transistor concept to directly obtain an output voltage while limiting a high burst current. Here, for a memory functionality of the SPT, defects in the gate oxide stack (i.e., Al₂O₃/HfO₂) deposited with thermal atomic layer deposition are playing the role of electron-trapping states. In addition, to achieve ultralow power consumption, an amorphous oxide semiconductor material (i.e., Hf-ZnO) with a wide bandgap is used for the channel while SPTs are always operated in the subthreshold region. For this, after SPTs are fabricated, the weight-update and retention characteristics are experimentally monitored verifying the concept. When positive pulses increasing the programming-pulse height are applied to the gate terminal, it is observed that the synaptic weight rapidly approaches its minimum value, which leads to a shorter retention time. This suggests the trade-off relation between the programming speed and retention characteristics. Here, as an approach to overcome the trade-off relation, repeated programming and retention monitoring experiments are also performed, leading to a much longer retention time of approximately 2 × 10⁴ s. In addition, the maximum static power consumption at read voltage is found to be 90 fW. Based on data in this SPT level, the analog accelerator simulation is also performed monitoring its performance (i.e., a recognition rate).