Effect of high-κ oxide dielectric deposition on the electrical performance and stability of p-channel CuI-based transistors

Abstract High- κ metal-oxide dielectrics are crucial for improving the electrical performance of thin-film transistors (TFTs) for low-voltage, low-power complementary metal-oxide semiconductor technologies. Copper iodide (CuI), a transparent p-type semiconductor compatible with commercial n-type oxides, shows promise for transparent complementary electronics. However, the inherently high hole concentration in pristine CuI channel leads to low mobility, poor on/off current ratios ( I on / I off ), and large subthreshold swing ( SS ). Traditional SiO 2 dielectric also leads to the high operating voltage, limiting low-power integration. Here, we systematically investigate the effects of atomic layer deposition (ALD) of high- κ Al 2 O 3 and HfO 2 dielectrics, deposited under varying conditions, on the electrical performance and bias stability of CuI-based TFTs. Results show that low-temperature (150 °C) deposited Al 2 O 3 and HfO 2 gate dielectrics improve hole mobility, I on / I off , and SS , while high-temperature (250 °C) deposition enhances bias stress stability by reducing defects and impurities. The TFT with a 150 °C HfO 2 gate dielectric achieved the best overall performance with an I on / I off of over 10 6 and a low SS of 80 mV/decade, approaching theoretical limits at room temperature. This work underscores the potential of high- κ dielectrics in developing low-voltage, stable CuI-based TFTs for advanced complementary electronics.