Asymmetric Voltage Latch Type and Ultra-Low Swing Bitline Sense Amplifiers for Low-Power High-Density 1R1W 8T SRAM in 14 nm FinFET

We propose two innovative sense amplifiers, the asymmetric voltage latched-type sense amplifier (A-VLSA) and the ultra-low swing bitline sense amplifier (ULS-SA), to enhance read performance and reduce power consumption in the non-hierarchical BL 2-port 8-transistor SRAM (2P-SRAM). A-VLSA minimizes offset voltage through a MOS capacitor-based asymmetric operation, while ULS-SA achieves reduced read power by adopting clipped precharging and a charge-sharing read mechanism without incurring delay penalties. Measurement results demonstrate that A-VLSA (ULS-SA) achieves 63% (37%) and 61% (63%) lower energy-delay product (EDP) at V<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>DD</b></sub> = 0.8V and 0.6V, respectively, with a 24% (43%) smaller area compared to the previous pseudo-differential asymmetric current latched-type sense amplifier (A-CLSA). These improvements address key limitations of prior approaches, delivering significant advancements in both power efficiency and read performance, especially under high cell density conditions.